Over the time, many processors operating in single instruction, multiple data (SIMD) (Reference 1) or multiple instructions, multiple data (MIMD) (Reference 2) style have been proposed. Many upcoming algorithms, like for example H.264, consist of a number of sub algorithms which follow partly the SIMD and partly the MIMD control style. Therefore, a number of different dual mode SIMD/MIMD architectures were developed (Reference 3-Reference 9). However, all these architectures have in common a complex data transfer network, which requires large amount of wiring area. An alternative approach was used inside the Cell processor, a processor which uses a pipelined ring bus as data network (Reference 10), which reduces the wiring area needs for the data transfer network.
All mentioned designs have in common, that the processing units (PU) are connected with the same bandwidth to the data transfer network. When however looking on nowadays complex algorithms, like for example H.264, it can be seen, that some parts of the algorithm require higher data bandwidth than other parts. Also, when looking on new arising architectures, like for example the one explained in Reference 11, different data bandwidth connections to the data transfer network can be observed for processing elements (PE) working in SIMD mode and autonomous working processing units (APU), which consist of four PE, working in MIMD mode.
The references are listed below.
[Reference 1]
    R. A. Stokes et al, “Parallel operating array computer”, U.S. Pat. No. 3,537,074, Oct. 27, 1970[Reference 2]    A. Rosman, “MIMD instruction flow computer architecture”, U.S. Pat. No. 4,837,676, Jun. 6, 1989[Reference 3]    R. J. Gove et al, “Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation”, U.S. Pat. No. 5,212,777, May 18, 1993[Reference 4]    N. K. Ing-Simmons et al, “Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode”, U.S. Pat. No. 5,239,654, Aug. 24, 1993[Reference 5]    R. J. Gove et al, “Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors”, U.S. Pat. No. 5,522,083, May 28, 1996[Reference 6]    J. A. Sgro et al, “Scalable multi-processor architecture for SIMD and MIMD operations”, U.S. Pat. No. 5,903,771, May 11, 1999[Reference 7]    T. Kan, “Parallel data processing system combining a SIMD unit with a MIMD unit and sharing a common bus, memory, and system controller”, U.S. Pat. No. 5,355,508, Oct. 11, 1994[Reference 8]    J. H. Jackson et al, “MIMD arrangement of SIMD machines”, U.S. Pat. No. 6,487,651, Nov. 26, 2002[Reference 9]    E. Waingold, “Baring it all to software: The Raw Machine”, MIT/LCS Technical Report TR-709, March 1997, pp. 1-28[Reference 10]    J. A. Kahle, “Introduction to the Cell multiprocessor”, IBM Journal of Research and Development Volume 49, Number 4/5, July/September 2005, pp. 589-604[Reference 11]    S. Kyo, “A Low Cost Mixed-mode Parallel Processor Architecture for Embedded Systems”, ICS, June 2007, pp. 253-262